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Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures
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Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures
Roy, Rabisankar
URI:
http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9986
Date:
2020-11
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Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures
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