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2. Ph.D Theses of IIT Kharagpur
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Electrical Engineering
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Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures
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Browsing Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures by Subject

Browsing Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures by Subject

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Subject
Constant power load [1]
Current-mode-control [1]
Intermediate bus architecture [1]
Limit cycle oscillation [1]
Point-of-load converter [1]

Now showing items 1-5 of 5

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