dc.contributor.author | Roy, Rabisankar | |
dc.date.accessioned | 2021-10-01T12:48:30Z | |
dc.date.available | 2021-10-01T12:48:30Z | |
dc.date.issued | 2020-11 | |
dc.identifier.govdoc | NB16886 | |
dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9986 | |
dc.language.iso | en_US | en_US |
dc.publisher | IIT Kharagpur | en_US |
dc.subject | Intermediate bus architecture | en_US |
dc.subject | Point-of-load converter | en_US |
dc.subject | Constant power load | en_US |
dc.subject | Current-mode-control | en_US |
dc.subject | Limit cycle oscillation | en_US |
dc.title | Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures | en_US |
dc.type | Thesis | en_US |