Test Infrastructure Design for Power Aware System-on-Chip Testing

dc.contributor.author	Giri, Chandan
dc.date.accessioned	2024-04-24T11:25:31Z
dc.date.available	2024-04-24T11:25:31Z
dc.date.issued	2008-01
dc.identifier.govdoc	NB13865
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13383
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Test Infrastructure Design	en_US
dc.subject	System-On-Chip	en_US
dc.subject	Test Architecture Optimization	en_US
dc.subject	Electronic Design	en_US
dc.title	Test Infrastructure Design for Power Aware System-on-Chip Testing	en_US
dc.type	Thesis	en_US