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  4. VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/1741
Title: VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer
Authors: Karim, Shaikh Montajul
Keywords: VLSI
Issue Date: Jun-2012
Publisher: IIT Kharagpur
Gov't Doc #: NB14685
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/1741
Appears in Collections:VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer

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