IDR - IIT Kharagpur

VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer

VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer

Karim, Shaikh Montajul
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/1741
Date: 2012-06

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