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http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14134| Title: | SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits |
| Authors: | Roy, Suchismita |
| Keywords: | Accurate Critical Delay Computation Bounded Delay Model Sequential Circuits Power Estimation Computing Critical Delay |
| Issue Date: | Jun-2007 |
| Publisher: | IIT Kharagpur |
| Gov't Doc #: | NB13465 |
| URI: | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14134 |
| Appears in Collections: | SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| NB13465_Thesis.pdf Restricted Access | 5.29 MB | Adobe PDF | View/Open Request a copy | |
| NB13465_Abstract.pdf | 1.5 MB | Adobe PDF | View/Open |
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