1. DSpace at My University
  2. 2. Ph.D Theses of IIT Kharagpur
  3. Computer Science & Engineering
  4. SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14134
Full metadata record
DC FieldValueLanguage
dc.contributor.authorRoy, Suchismita-
dc.date.accessioned2024-05-09T07:13:19Z-
dc.date.available2024-05-09T07:13:19Z-
dc.date.issued2007-06-
dc.identifier.govdocNB13465-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14134-
dc.language.isoenen_US
dc.publisherIIT Kharagpuren_US
dc.subjectAccurate Critical Delay Computationen_US
dc.subjectBounded Delay Modelen_US
dc.subjectSequential Circuitsen_US
dc.subjectPower Estimationen_US
dc.subjectComputing Critical Delayen_US
dc.titleSAT Based Solutions for Timing and Power Estimation of Gate Level Circuitsen_US
dc.typeThesisen_US
Appears in Collections:SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits

Files in This Item:
File Description SizeFormat 
NB13465_Thesis.pdf
  Restricted Access		5.29 MBAdobe PDFView/Open Request a copy
NB13465_Abstract.pdf1.5 MBAdobe PDFView/Open
Show simple item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.