SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits Collection home page

Author: Suchismita Roy
Supervisors: Prof. P.P. Chakrabarti and Prof. Pallab Dasgupta
Department of Computer Science and Engineering
Indian Institute of Technology Kharagpur, India
June, 2007

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Collection's Items (Sorted by Submit Date in Descending order): 1 to 1 of 1
Issue DateTitleAuthor(s)
2007-06SAT Based Solutions for Timing and Power Estimation of Gate Level CircuitsRoy, Suchismita
Collection's Items (Sorted by Submit Date in Descending order): 1 to 1 of 1