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Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
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Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
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Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
Som, Indranil
URI:
http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9646
Date:
2020-06
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Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
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