Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process

dc.contributor.author	Som, Indranil
dc.date.accessioned	2021-07-12T05:36:30Z
dc.date.available	2021-07-12T05:36:30Z
dc.date.issued	2020-06
dc.identifier.govdoc	NB16709
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9646
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Clock and data recovery (CDR)	en_US
dc.subject	Clock Synthesizers	en_US
dc.subject	Signal integrity	en_US
dc.subject	Dual loop architecture	en_US
dc.subject	Linear operating span	en_US
dc.title	Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process	en_US
dc.type	Thesis	en_US