IDR - IIT Kharagpur

Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process

Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process

 

Author: Indranil Som
Supervisor: Prof. T. K. Bhattacharyya
Department of Electronics and Electrical Communication Engineering
Indian Institute of Technology Kharagpur, India
June, 2020

Recent Submissions