Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process

Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process http://127.0.0.1/xmlui/handle/123456789/9645 2026-04-17T13:36:09Z 2026-04-17T13:36:09Z Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process Som, Indranil http://127.0.0.1/xmlui/handle/123456789/9646 2021-07-12T05:36:57Z 2020-06-01T00:00:00Z

Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process Som, Indranil

2020-06-01T00:00:00Z