Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process

Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process http://127.0.0.1/xmlui/handle/123456789/9645 Fri, 17 Apr 2026 10:50:35 GMT 2026-04-17T10:50:35Z Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process http://127.0.0.1/xmlui/handle/123456789/9646 Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process Som, Indranil Mon, 01 Jun 2020 00:00:00 GMT http://127.0.0.1/xmlui/handle/123456789/9646 2020-06-01T00:00:00Z