IDR - IIT Kharagpur
VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer
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| dc.contributor.author | Karim, Shaikh Montajul | |
| dc.date.accessioned | 2013-03-25T07:44:35Z | |
| dc.date.available | 2013-03-25T07:44:35Z | |
| dc.date.issued | 2012-06 | |
| dc.identifier.govdoc | NB14685 | |
| dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/1741 | |
| dc.language.iso | en | en |
| dc.publisher | IIT Kharagpur | en |
| dc.subject | VLSI | en |
| dc.title | VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer | en |
| dc.type | Thesis | en |
