IDR - IIT Kharagpur
Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process
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| dc.contributor.author | Sarangi, Santunu | |
| dc.date.accessioned | 2023-04-12T06:37:04Z | |
| dc.date.available | 2023-04-12T06:37:04Z | |
| dc.date.issued | 2022-12 | |
| dc.identifier.govdoc | NB17661 | |
| dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/12746 | |
| dc.language.iso | en | en_US |
| dc.publisher | IIT Kharagpur | en_US |
| dc.subject | High-Speed System Design | en_US |
| dc.subject | Serdes System | en_US |
| dc.subject | 65 nm CMOS Process | en_US |
| dc.subject | Jitter Measurement Circuit | en_US |
| dc.subject | Phase-Locked Loops | en_US |
| dc.title | Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process | en_US |
| dc.type | Thesis | en_US |
