IDR - IIT Kharagpur

Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process

Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process

 

Author: Santunu Sarangi
Supervisor: Prof. T. K. Bhattacharyya
Electronics and Electrical Communication Engineering
Indian Institute of Technology Kharagpur, India
December, 2022

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