Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process

Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process http://127.0.0.1/xmlui/handle/123456789/12745 2026-04-18T02:55:51Z 2026-04-18T02:55:51Z Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process Sarangi, Santunu http://127.0.0.1/xmlui/handle/123456789/12746 2023-04-12T06:37:27Z 2022-12-01T00:00:00Z

Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process Sarangi, Santunu

2022-12-01T00:00:00Z