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  4. Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9646
Title: Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
Authors: Som, Indranil
Keywords: Clock and data recovery (CDR)
Clock Synthesizers
Signal integrity
Dual loop architecture
Linear operating span
Issue Date: Jun-2020
Publisher: IIT Kharagpur
Gov't Doc #: NB16709
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9646
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