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  4. Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9646
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dc.contributor.authorSom, Indranil-
dc.date.accessioned2021-07-12T05:36:30Z-
dc.date.available2021-07-12T05:36:30Z-
dc.date.issued2020-06-
dc.identifier.govdocNB16709-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9646-
dc.language.isoenen_US
dc.publisherIIT Kharagpuren_US
dc.subjectClock and data recovery (CDR)en_US
dc.subjectClock Synthesizersen_US
dc.subjectSignal integrityen_US
dc.subjectDual loop architectureen_US
dc.subjectLinear operating spanen_US
dc.titleDesign and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Processen_US
dc.typeThesisen_US
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