DSpace at My University: Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process

Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process Collection home page

Author: Indranil Som
Supervisor: Prof. T. K. Bhattacharyya
Department of Electronics and Electrical Communication Engineering
Indian Institute of Technology Kharagpur, India
June, 2020

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Issue Date	Title	Author(s)
2020-06	Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process	Som, Indranil

Collection's Items (Sorted by Submit Date in Descending order): 1 to 1 of 1

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Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process Collection home page

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