Thermal-Aware Design and Test Techniques for Two- and Three-Dimensional Networks-on-Chip

dc.contributor.author	Manna, Kanchan
dc.date.accessioned	2016-03-04T07:02:22Z
dc.date.available	2016-03-04T07:02:22Z
dc.date.issued	2016-02
dc.identifier.govdoc	NB15405
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/6182
dc.language.iso	en	en
dc.publisher	IIT, Kharagpur	en
dc.subject	Three Dimensional NoC (3D-NoC)	en
dc.subject	Network-on-Chip (NoC)	en
dc.subject	Particle Swarm Optimization (PSO)	en
dc.subject	Kerninghan-Lin (KL) Partitioning	en
dc.subject	Thermal-Aware Mapping	en
dc.title	Thermal-Aware Design and Test Techniques for Two- and Three-Dimensional Networks-on-Chip	en
dc.type	Thesis	en