SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits

dc.contributor.author	Roy, Suchismita
dc.date.accessioned	2024-05-09T07:13:19Z
dc.date.available	2024-05-09T07:13:19Z
dc.date.issued	2007-06
dc.identifier.govdoc	NB13465
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14134
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Accurate Critical Delay Computation	en_US
dc.subject	Bounded Delay Model	en_US
dc.subject	Sequential Circuits	en_US
dc.subject	Power Estimation	en_US
dc.subject	Computing Critical Delay	en_US
dc.title	SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits	en_US
dc.type	Thesis	en_US