IDR - IIT Kharagpur

SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits

SAT Based Solutions for Timing and Power Estimation of Gate Level Circuits

 

Author: Suchismita Roy
Supervisors: Prof. P.P. Chakrabarti and Prof. Pallab Dasgupta
Department of Computer Science and Engineering
Indian Institute of Technology Kharagpur, India
June, 2007

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