Hardware-Efficient VLSI Architectures and Algorithms For The HEVC Standard

dc.contributor.author	Singhadia, Ashish
dc.date.accessioned	2022-11-10T10:25:05Z
dc.date.available	2022-11-10T10:25:05Z
dc.date.issued	2022-02
dc.identifier.govdoc	NB17343
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/12096
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	HEVC	en_US
dc.subject	Deblocking Filter	en_US
dc.subject	Sample Adaptive Offset	en_US
dc.subject	Rate Control	en_US
dc.subject	Adaptive Quantization	en_US
dc.title	Hardware-Efficient VLSI Architectures and Algorithms For The HEVC Standard	en_US
dc.type	Thesis	en_US