Quantum Circuit Realization, Optimization and Placement with Improved Fault-Tolerance

dc.contributor.author	Kole, Abhoy
dc.date.accessioned	2022-08-25T05:07:32Z
dc.date.available	2022-08-25T05:07:32Z
dc.date.issued	2021-07
dc.identifier.govdoc	NB17130
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11683
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Quantum circuit compilation	en_US
dc.subject	Decomposition	en_US
dc.subject	Nearest neighbor mapping	en_US
dc.subject	Optimization	en_US
dc.subject	Fault-Tolerance	en_US
dc.title	Quantum Circuit Realization, Optimization and Placement with Improved Fault-Tolerance	en_US
dc.type	Thesis	en_US