Design of Low Vmin Area Efficient Compiler Compatible 1R1W Register Files for Future SoCs

dc.contributor.author	Ghosh, Arindrajit
dc.date.accessioned	2022-03-30T06:52:35Z
dc.date.available	2022-03-30T06:52:35Z
dc.date.issued	2018-03
dc.identifier.govdoc	NB16020
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/10749
dc.language.iso	en_US	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	1R1W	en_US
dc.subject	SoC	en_US
dc.subject	High density	en_US
dc.subject	Ultra-high density	en_US
dc.subject	Contention free delayed keeper	en_US
dc.title	Design of Low Vmin Area Efficient Compiler Compatible 1R1W Register Files for Future SoCs	en_US
dc.type	Thesis	en_US