IDR - IIT Kharagpur

Design of Low Vmin Area Efficient Compiler Compatible 1R1W Register Files for Future SoCs

Design of Low Vmin Area Efficient Compiler Compatible 1R1W Register Files for Future SoCs

 

Author: Arindrajit Ghosh
Supervisors: Dr. Swapna Banerjee and Dr. Uddalak Bhattacharya
Department of Electronics and Electrical Communication Engineering
Indian Institute of Technology Kharagpur, India
March, 2018

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