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  4. Thermal-Aware Design and Test Techniques for Two- and Three-Dimensional Networks-on-Chip
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/6182
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dc.contributor.authorManna, Kanchan-
dc.date.accessioned2016-03-04T07:02:22Z-
dc.date.available2016-03-04T07:02:22Z-
dc.date.issued2016-02-
dc.identifier.govdocNB15405-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/6182-
dc.language.isoenen
dc.publisherIIT, Kharagpuren
dc.subjectThree Dimensional NoC (3D-NoC)en
dc.subjectNetwork-on-Chip (NoC)en
dc.subjectParticle Swarm Optimization (PSO)en
dc.subjectKerninghan-Lin (KL) Partitioningen
dc.subjectThermal-Aware Mappingen
dc.titleThermal-Aware Design and Test Techniques for Two- and Three-Dimensional Networks-on-Chipen
dc.typeThesisen
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