DSpace JSPUI
DSpace preserves and enables easy and open access to all types of digital content including text, images, moving images, mpegs and data sets
Learn More
Please use this identifier to cite or link to this item:
http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/2079| Title: | Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits |
| Authors: | Mitra, Srobona |
| Keywords: | Digital Integrated Circuits MODEL CHECKING FORMAL METHODS FORMAL VERIFICATION EQUIVALENCE CHECKING |
| Issue Date: | Jun-2013 |
| Publisher: | IIT Kharagpur |
| Gov't Doc #: | NB14805 |
| URI: | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/2079 |
| Appears in Collections: | Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| NB14805_Thesis.pdf Restricted Access | 2.21 MB | Adobe PDF | View/Open Request a copy | |
| NB14805_Introduction.pdf | 608.22 kB | Adobe PDF |  View/Open | |
| NB14805_Content.pdf | 448.61 kB | Adobe PDF |  View/Open | |
| NB14805_Bibliography.pdf | 539.5 kB | Adobe PDF |  View/Open | |
| NB14805_Abstract.pdf | 420.5 kB | Adobe PDF |  View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.