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Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits
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Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits
Mitra, Srobona
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http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/2079
Date:
2013-06
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Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits
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