1. DSpace at My University
  2. 2. Ph.D Theses of IIT Kharagpur
  3. Computer Science & Engineering
  4. Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/2079
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMitra, Srobona
dc.date.accessioned2014-05-27T07:25:55Z
dc.date.available2014-05-27T07:25:55Z
dc.date.issued2013-06
dc.identifier.govdocNB14805
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/2079
dc.language.isoenen
dc.publisherIIT Kharagpuren
dc.subjectDigital Integrated Circuitsen
dc.subjectMODEL CHECKINGen
dc.subjectFORMAL METHODSen
dc.subjectFORMAL VERIFICATIONen
dc.subjectEQUIVALENCE CHECKINGen
dc.titleFormal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuitsen
dc.typeThesisen
Appears in Collections:Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits

Files in This Item:
File Description SizeFormat 
NB14805_Thesis.pdf
  Restricted Access		2.21 MBAdobe PDFView/Open Request a copy
NB14805_Introduction.pdf608.22 kBAdobe PDFThumbnail
View/Open
NB14805_Content.pdf448.61 kBAdobe PDFThumbnail
View/Open
NB14805_Bibliography.pdf539.5 kBAdobe PDFThumbnail
View/Open
NB14805_Abstract.pdf420.5 kBAdobe PDFThumbnail
View/Open
Show simple item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.