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Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338
Title: Low Power Logic Optimization and Synthesis
Authors: Chaudhury, Saurabuh
Keywords: Circuits
Power Optimization
CMOS VLSI Circuits
Low Power Dissipation
Issue Date: 2009
Publisher: IIT Kharagpur
Gov't Doc #: NB13905
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338
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