Please use this identifier to cite or link to this item:
http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338
Title: | Low Power Logic Optimization and Synthesis |
Authors: | Chaudhury, Saurabuh |
Keywords: | Circuits Power Optimization CMOS VLSI Circuits Low Power Dissipation |
Issue Date: | 2009 |
Publisher: | IIT Kharagpur |
Gov't Doc #: | NB13905 |
URI: | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338 |
Appears in Collections: | Low Power Logic Optimization and Synthesis |
Files in This Item:
File | Description | Size | Format | |
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NB13905_Abstract.pdf | 1.03 MB | Adobe PDF | View/Open | |
NB13905_Thesis.pdf Restricted Access | 4.2 MB | Adobe PDF | View/Open Request a copy |
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