Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338
Title: Low Power Logic Optimization and Synthesis
Authors: Chaudhury, Saurabuh
Keywords: Circuits
Power Optimization
CMOS VLSI Circuits
Low Power Dissipation
Issue Date: 2009
Publisher: IIT Kharagpur
Gov't Doc #: NB13905
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338
Appears in Collections:Low Power Logic Optimization and Synthesis

Files in This Item:
File Description SizeFormat 
NB13905_Abstract.pdf1.03 MBAdobe PDFView/Open
NB13905_Thesis.pdf
  Restricted Access
4.2 MBAdobe PDFView/Open Request a copy


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.