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  4. Low Power Logic Optimization and Synthesis
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338
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dc.contributor.authorChaudhury, Saurabuh-
dc.date.accessioned2024-04-24T10:18:29Z-
dc.date.available2024-04-24T10:18:29Z-
dc.date.issued2009-
dc.identifier.govdocNB13905-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338-
dc.language.isoenen_US
dc.publisherIIT Kharagpuren_US
dc.subjectCircuitsen_US
dc.subjectPower Optimizationen_US
dc.subjectCMOS VLSI Circuitsen_US
dc.subjectLow Power Dissipationen_US
dc.titleLow Power Logic Optimization and Synthesisen_US
dc.typeThesisen_US
Appears in Collections:Low Power Logic Optimization and Synthesis

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