Please use this identifier to cite or link to this item:
http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/12096
Title: | Hardware-Efficient VLSI Architectures and Algorithms For The HEVC Standard |
Authors: | Singhadia, Ashish |
Keywords: | HEVC Deblocking Filter Sample Adaptive Offset Rate Control Adaptive Quantization |
Issue Date: | Feb-2022 |
Publisher: | IIT Kharagpur |
Gov't Doc #: | NB17343 |
URI: | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/12096 |
Appears in Collections: | Hardware-Efficient VLSI Architectures and Algorithms For The HEVC Standard |
Files in This Item:
File | Description | Size | Format | |
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NB17343_Abstract.pdf | 66.78 kB | Adobe PDF | View/Open | |
NB17343_Thesis.pdf Restricted Access | 5.35 MB | Adobe PDF | View/Open Request a copy |
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