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  4. Hardware-Efficient VLSI Architectures and Algorithms For The HEVC Standard
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/12096
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dc.contributor.authorSinghadia, Ashish-
dc.date.accessioned2022-11-10T10:25:05Z-
dc.date.available2022-11-10T10:25:05Z-
dc.date.issued2022-02-
dc.identifier.govdocNB17343-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/12096-
dc.language.isoenen_US
dc.publisherIIT Kharagpuren_US
dc.subjectHEVCen_US
dc.subjectDeblocking Filteren_US
dc.subjectSample Adaptive Offseten_US
dc.subjectRate Controlen_US
dc.subjectAdaptive Quantizationen_US
dc.titleHardware-Efficient VLSI Architectures and Algorithms For The HEVC Standarden_US
dc.typeThesisen_US
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