IDR - IIT Kharagpur
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2. Ph.D Theses of IIT Kharagpur
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Electronics & Electrical Communication Engineering
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Design and Implementation of 12.5 Gb/s Linear Clock and Data Recovery Circuit using 65 nm CMOS Process
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Clock and data recovery (CDR) (1)
Clock Synthesizers (1)
Dual loop architecture (1)
Linear operating span (1)
Signal integrity (1)
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