Genetic Algorithm based Logic Optimization and Synthesis Techniques with Area-Power Trade-offs

Abstract

In recent times, power consumption has been recognized as an important issue in implementing battery-operated portable devices. Power consumption of individual blocks of VLSI circuit is reaching the limits of what can be dealt with by economic packaging technologies, resulting in the reduction of chip reliability. As a result, power consumption is being addressed in all levels of VLSI design hierarchy. Obviously, the saving will be higher if power issues are taken care of early in the design cycle. This has motivated us to consider power issue at the logic level. Though dynamic power is still the major source of power consumption, aggressive technology scaling to get the required performance with reduced production cost has the side effect of increasing the transistor leakage current. Due to the exponential nature of leakage current in the subthreshold regime operation of transistors, leakage current can no longer be ignored. In this thesis we have addressed both the dynamic and leakage power consumption of the circuit.