dc.contributor.author	Mitra, Srobona
dc.date.accessioned	2014-05-27T07:25:55Z
dc.date.available	2014-05-27T07:25:55Z
dc.date.issued	2013-06
dc.identifier.govdoc	NB14805
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/2079
dc.language.iso	en	en
dc.publisher	IIT Kharagpur	en
dc.subject	Digital Integrated Circuits	en
dc.subject	MODEL CHECKING	en
dc.subject	FORMAL METHODS	en
dc.subject	FORMAL VERIFICATION	en
dc.subject	EQUIVALENCE CHECKING	en
dc.title	Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits	en
dc.type	Thesis	en

Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits

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