IDR - IIT Kharagpur

FPGA Fabric Conscious Architecture Design and Inclusion of Testability for High Performance Implementations

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dc.contributor.author Palchaudhuri, Ayan
dc.date.accessioned 2022-09-29T04:35:18Z
dc.date.available 2022-09-29T04:35:18Z
dc.date.issued 2021-11
dc.identifier.govdoc NB17262
dc.identifier.uri http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11941
dc.language.iso en en_US
dc.publisher IIT Kharagpur en_US
dc.subject Field Programmable Gate Arrays en_US
dc.subject Primitive instantiation en_US
dc.subject Hardware description language en_US
dc.subject Look-up table en_US
dc.subject Carry chain en_US
dc.title FPGA Fabric Conscious Architecture Design and Inclusion of Testability for High Performance Implementations en_US
dc.type Thesis en_US


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