Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/7831
Title: A Class of Pipelined Architectures to Realize High Speed Adaptive Equalizers
Authors: Pervin, Suraiya
Keywords: Zero Latency
Pipelined Architecture
Karhmen Loeve Transform
Systolic Array
Adaptive Equalizer
Issue Date: 1-Dec-2001
Publisher: IIT, Kharagpur
Gov't Doc #: NB12731
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/7831
Appears in Collections:A Class of Pipelined Architectures to Realize High Speed Adaptive Equalizers

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