Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/7831
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dc.contributor.authorPervin, Suraiya-
dc.date.accessioned2017-07-14T05:20:03Z-
dc.date.available2017-07-14T05:20:03Z-
dc.date.issued2001-12-01-
dc.identifier.govdocNB12731-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/7831-
dc.language.isoenen
dc.publisherIIT, Kharagpuren
dc.subjectZero Latencyen
dc.subjectPipelined Architectureen
dc.subjectKarhmen Loeve Transformen
dc.subjectSystolic Arrayen
dc.subjectAdaptive Equalizeren
dc.titleA Class of Pipelined Architectures to Realize High Speed Adaptive Equalizersen
dc.typeThesisen
Appears in Collections:A Class of Pipelined Architectures to Realize High Speed Adaptive Equalizers

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