New Techniques in Testing and Timing Verification of System-on-Chips

Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/633

Full metadata record

DC Field	Value	Language
dc.contributor.author	Chakraborty, Rupsa
dc.date.accessioned	2010-07-07T11:07:05Z
dc.date.available	2010-07-07T11:07:05Z
dc.date.issued	2010
dc.identifier.govdoc	NB14212
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/633
dc.description.abstract	THE PRIMARY CHALLENGE during the modern integrated circuit development process lies in coping with the progressively shorter time-to-market of the chips. Modular design through design re-use in the System-on-Chip (SoC) technology though aids in reducing the design time, the process of testing and verification of such highly complex circuits turns out to be more challenging.	en
dc.language.iso	en	en
dc.publisher	IIT Kharagpur	en
dc.subject	System-on-Chips	en
dc.title	New Techniques in Testing and Timing Verification of System-on-Chips	en
dc.type	Thesis	en
Appears in Collections:	New Techniques in Testing and Timing Verification of System-on-Chips

Files in This Item:

File	Description	Size	Format
NB14212.pdf Restricted Access	Not Downloadable PDF File	3.91 MB	Adobe PDF	View/Open Request a copy
NB14212_Abstract.pdf	Downloadable PDF File	241.63 kB	Adobe PDF	View/Open
NB14212_CV.pdf	Downloadable PDF File	275.79 kB	Adobe PDF	View/Open
NB14212_Introduction.pdf	Downloadable PDF File	339.13 kB	Adobe PDF	View/Open
NB14212_TOC.pdf	Downloadable PDF File	291.23 kB	Adobe PDF	View/Open

DSpace JSPUI