Please use this identifier to cite or link to this item:
http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5542
Title: | Formal Methods for Architectural Power Intent Verification and Functional Reliability Analysis |
Authors: | Hazra, Aritra |
Keywords: | VLSI Reliability VLSI / Integrated Cir- cuits Power Management Formal Verification |
Issue Date: | Mar-2015 |
Publisher: | IIT, Kharagpur |
Gov't Doc #: | NB15171 |
URI: | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5542 |
Appears in Collections: | Formal Methods for Architectural Power Intent Verification and Functional Reliability Analysis |
Files in This Item:
File | Description | Size | Format | |
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NB15171_Abstract.pdf | 33.38 kB | Adobe PDF | ![]() View/Open | |
NB15171_Thesis.pdf Restricted Access | 1.99 MB | Adobe PDF | View/Open Request a copy |
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