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  4. Formal Methods for Architectural Power Intent Verification and Functional Reliability Analysis
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5542
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dc.contributor.authorHazra, Aritra-
dc.date.accessioned2015-11-17T05:44:04Z-
dc.date.available2015-11-17T05:44:04Z-
dc.date.issued2015-03-
dc.identifier.govdocNB15171-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5542-
dc.language.isoenen
dc.publisherIIT, Kharagpuren
dc.subjectVLSIen
dc.subjectReliabilityen
dc.subjectVLSI / Integrated Cir- cuitsen
dc.subjectPower Managementen
dc.subjectFormal Verificationen
dc.titleFormal Methods for Architectural Power Intent Verification and Functional Reliability Analysisen
dc.typeThesisen
Appears in Collections:Formal Methods for Architectural Power Intent Verification and Functional Reliability Analysis

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