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  4. Improved Test Techniques for Network-on-Chip Based Memory Systems
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5073
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dc.contributor.authorGhoshal, Bibhas-
dc.date.accessioned2015-09-23T04:48:04Z-
dc.date.available2015-09-23T04:48:04Z-
dc.date.issued2014-07-
dc.identifier.govdocNB15125-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5073-
dc.language.isoenen
dc.publisherIIT Kharagpuren
dc.subjectFIFO Bufferen
dc.subjectDRAM Operationen
dc.subjectSRAM Operationen
dc.subjectMemory BISTen
dc.subjectNetwork-on-Chipen
dc.titleImproved Test Techniques for Network-on-Chip Based Memory Systemsen
dc.typeThesisen
Appears in Collections:Improved Test Techniques for Network-on-Chip Based Memory Systems

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