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  4. Performance Enhancement of a Pipeline Analog-to-Digital Converter Through Topological Modification of Building Blocks
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/3907
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dc.contributor.authorRoy, Sounak-
dc.date.accessioned2015-06-26T11:13:09Z-
dc.date.available2015-06-26T11:13:09Z-
dc.date.issued2015-06-26T11:13:09Z-
dc.identifier.govdocNB15051-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/3907-
dc.language.isoenen
dc.subjectDigital Calibration of Pipeline ADCen
dc.subjectDigital Error Correctionen
dc.subjectBottom Plate Samplingen
dc.subjectDouble Samplingen
dc.subjectTime Interleavingen
dc.subjectPipeline ADCen
dc.titlePerformance Enhancement of a Pipeline Analog-to-Digital Converter Through Topological Modification of Building Blocksen
dc.typeThesisen
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