Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14963
Title: A Machine Learning Approach for Network-on-Chip Architecture Design
Authors: Sambangi, Ramesh
Keywords: Network-On-Chip(Noc)
Noc Analytical Model
Application Mapping
Machine Learning
Message Passing Neural Network (MPNN)
Issue Date: Feb-2024
Publisher: IIT Kharagpur
Gov't Doc #: NB18156
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14963
Appears in Collections:A Machine Learning Approach for Network-on-Chip Architecture Design

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