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  4. A Machine Learning Approach for Network-on-Chip Architecture Design
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14963
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dc.contributor.authorSambangi, Ramesh-
dc.date.accessioned2024-08-05T09:44:28Z-
dc.date.available2024-08-05T09:44:28Z-
dc.date.issued2024-02-
dc.identifier.govdocNB18156-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14963-
dc.language.isoenen_US
dc.publisherIIT Kharagpuren_US
dc.subjectNetwork-On-Chip(Noc)en_US
dc.subjectNoc Analytical Modelen_US
dc.subjectApplication Mappingen_US
dc.subjectMachine Learningen_US
dc.subjectMessage Passing Neural Network (MPNN)en_US
dc.titleA Machine Learning Approach for Network-on-Chip Architecture Designen_US
dc.typeThesisen_US
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