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  4. Algorithms and Architectures for Structured Low Density Parity Check Codes
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11577
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dc.contributor.authorShantharam, Kalipatnapu-
dc.date.accessioned2022-08-10T06:37:26Z-
dc.date.available2022-08-10T06:37:26Z-
dc.date.issued2020-02-
dc.identifier.govdocNB17075-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11577-
dc.language.isoenen_US
dc.publisherIIT Kharagpuren_US
dc.subjectLow Density Parity Check (LDPC) Codesen_US
dc.subjectBinary compressed sensingen_US
dc.subjectLow complexity VLSI Architectureen_US
dc.subjectBit flipping decoderen_US
dc.subjectNon-Binary LDPCen_US
dc.titleAlgorithms and Architectures for Structured Low Density Parity Check Codesen_US
dc.typeThesisen_US
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